In recent years, it is requested in the field of a semiconductor integrated circuit that the variability of a substrate voltage of the semiconductor integrated circuit resulting from PVT (process, voltage variation, temperature) be reduced based on the control of a substrate voltage of an MOS element for supplying the substrate voltage so as to realize an optimum delay setting and cut down power consumption. In order to realize the request, it is necessary to provide a substrate voltage control circuit for monitoring a characteristic of the MOS element for supplying the substrate voltage and supplying an optimum substrate voltage conformable to an actual delay value to the semiconductor integrated circuit via the MOS element for supplying the substrate voltage. There are two conventional circuits which realized such substrate voltage control.
The first conventional example is a constitution wherein the substrate voltage is supplied to the semiconductor integrated circuit via the MOS element for supplying the substrate voltage so that a saturation current of the MOS element for supplying the substrate voltage can be constant, which is recited in the Non-Patent Document 1. A schematic illustration of the example is shown in FIG. 12.
The second conventional example is a constitution wherein a delay of a replica circuit having the same circuit configuration as that of a circuit to be controlled is monitored, and such a substrate voltage that a delay value thereby obtained can be optimal is supplied to the actual circuit (semiconductor integrated circuit), which is recited in the Non-Patent Document 2.    Non-Patent Document 1: (M. Sumita, S. Sakiyama, M. Kinoshita, Y. Araki, Y. Ikeda, and K. Fukuoka, “MixedBody Bias Techniques with Fixed Vt and Ids Generation Circuits” ISSCC Digest of Technical Papers, pp. 158-159, February 2004)    Non-Patent Document 2: (J. Tschanz, J. Kao, S. Narendra, R. Nair, dantoniadis, A. Chandrakasan, and V. De, “Adaptive Body Bias for Reducing Impacts of Die-to-Die and Within-DieParameter Variation on Microprocessor Frequency and Leakage” ISSCC Digest of Technical Papers, pp. 412-413, February 2002.)